Pinouts Description

A1

PRSNT1#

Mechanical Present

B1

12V

A2

12V

B2

12V

A3

12V

B3

12V

A4

GND

B4

GND

A5

TCK

JTAG - Not Connected

B5

SMCLK

Host SMBus

A6

TDI

JTAG - Not Connected

B6

SMDAT

Host SMBus

A7

TDO

JTAG - Not Connected

B7

GND

A8

TMS

JTAG - Not Connected

B8

3.3V

3.3V - (Connected in 900-9D3B4-00CC-EA0 & 900-9D3B4-00SC-EA0 only)

A9

3.3V

3.3V - (Connected in 900-9D3B4-00CC-EA0 & 900-9D3B4-00SC-EA0 only)

B9

TRST#

JTAG - Not Connected

A10

3.3V

3.3V - (Connected in 900-9D3B4-00CC-EA0 & 900-9D3B4-00SC-EA0 only)

B10

3.3V_AUX

A11

PERST#

PCIe Reset

B11

WAKW#/RSVD

A12

GND

B12

SER_DI 

A13

REFCLK+

Host Reference Clock

B13

GND

A14

REFCLK-

Host Reference Clock

B14

PETP0

A15

GND

B15

PETN0

A16

PERP0

B16

GND

A17

PERN0

B17

RSVD

A18

GND

B18

GND

A19

SER_DO

B19

PETP1

A20

GND

B20

PETN1

A21

PERP1

B21

GND

A22

PERN1

B22

GND

A23

GND

B23

PETP2

A24

GND

B24

PETN2

A25

PERP2

B25

GND

A26

PERN2

B26

GND

A27

GND

B27

PETP3

A28

GND

B28

PETN3

A29

PERP3

B29

GND

A30

PERN3

B30

RSVD

A31

GND

B31

RSVD

A32

SER_CLK

B32

GND

A33

SER_CAPTURE    

B33

PETP4

A34

GND

B34

PETN4

A35

PERP4

B35

GND

A36

PERN4

B36

GND

A37

GND

B37

PETP5

A38

GND

B38

PETN5

A39

PERP5

B39

GND

A40

PERN5

B40

GND

A41

GND

B41

PETP6

A42

GND

B42

PETN6

A43

PERP6

B43

GND

A44

PERN6

B44

GND

A45

GND

B45

PETP7

A46

GND

B46

PETN7

A47

PERP7

B47

GND

A48

PERN7

B48

RSVD

A49

GND

B49

GND

A50

RSVD

B50

PETP8

A51

GND

B51

PETN8

A52

PERP8

B52

GND

A53

PERN8

B53

GND

A54

GND

B54

PETP9

A55

GND

B55

PETN9

A56

PERP9

B56

GND

A57

PERN9

B57

GND

A58

GND

B58

PETP10

A59

GND

B59

PETN10

A60

PERP10

B60

GND

A61

PERN10

B61

GND

A62

GND

B62

PETP11

A63

GND

B63

PETN11

A64

PERP11

B64

GND

A65

PERN11

B65

GND

A66

GND

B66

PETP12

A67

GND

B67

PETN12

A68

PERP12

B68

GND

A69

PERN12

B69

GND

A70

GND

B70

PETP13

A71

GND

B71

PETN13

A72

PERP13

B72

GND

A73

PERN13

B73

GND

A74

GND

B74

PETP14

A75

GND

B75

PETN14

A76

PERP14

B76

GND

A77

PERN14

B77

GND

A78

GND

B78

PETP15

A79

GND

B79

PETN15

A80

PERP15

B80

GND

A81

PERN15

B81

PRSNT2#

Mechanical Present

A82

GND

B82

GND

1

12V

2

12V

3

12V

4

Sense1

5

GND

6

Sense0

7

GND

8

GND

1

GND

GND

Ground

2

PKG_ID1

Input (to BlueField-3)

NC-SI PKG_ID

Should be connected to the Primary controller NC-SI PKG_ID pins to set the appropriate package ID.

PKG_ID0 should be connected to the endpoint device GPIO associated with Package ID[0]. PKG_ID1 should be associated with Package ID[1].

Baseboard should connect to GND or leave floating.

DPU should have a 4.7k PU.

3

RBT_RXD0

Output (from BlueField-3)

Receive data. Data signals from the network controller to the BMC.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to GND on the baseboard between the BMC and the RBT isolator to prevent the signal from floating when no card is installed.

For DPUs, this pin should be connected between the connector and the RBT PHY.  External termination determined by the DPU RBT PHY requirements.

4

RBT_REF_CLK

Input

RBT Reference clock. Synchronous clock reference for receive, transmit and control interface. The clock should have a typical frequency of 50MHz ±50 ppm.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the DPU  cable connector. The RBT_REF_CLK should not be driven until 3.3V AUX is present on the DPU. The RBT_REF_CLK should be continuous once it has started.

For DPUs, this pin should be connected between the connector and the RBT PHY.  No external termination is required.

5

RBT_RXD1

Output

Receive data. Data signals from the network controller to the BMC.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to GND on the baseboard between the BMC and the RBT isolator to prevent the signal from floating when no card is installed.

For DPUs, this pin should be connected between the connector and the RBT PHY.  External termination determined by the DPU RBT PHY requirements.

6

GND

GND

Ground

7

RBT_CRS_DV

Output

Carrier sense/receive data valid. This signal is used to indicate to the baseboard that the carrier sense/receive data is valid.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor on the baseboard between the BMC and the RBT isolator to prevent the signal from floating when no DPU is installed.

For DPUs, this pin should be connected between the connector and the RBT PHY.  External termination determined by the DPU RBT PHY requirements.

8

RBT_ISOLATE_N

Output

This signal is used to indicate the DPU has powered and is ready for NC-SI physical layer connection to be present.  When low the baseboard circuitry will isolate the NC-SI connection to the DPU.  When high normal NC-SI RBT connectivity is available.

Baseboards should terminate this with a 47K-100K PD resistor.

DPUs should terminate with a 10k PU resistor.

9

GND

GND

Ground

10

PKG_ID0

Input

NC-SI PKG_ID

should be connected to the Primary controller NC-SI PKG_ID pins to set the appropriate package ID.

PKG_ID0 should be connected to the endpoint device GPIO associated with Package ID[0]. PKG_ID1 should be associated with Package ID[1].

Baseboard should connect to GND or leave floating.

DPU should have a 4.7k PU.

11

RBT_TX_EN

Input

Transmit enable.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to ground on the baseboard between the RBT isolator and the DPU cable connector to prevent the card-side signals from floating when the RBT signals are isolated. 

For DPUs, this pin should be connected between the connector and the RBT PHY.  External termination determined by the DPU RBT PHY requirements.

12

GND

GND

Ground

13

RBT_TXD0

Input

Transmit data. Data signals from the BMC to the network controller.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to GND on the baseboard between the RBT isolator and the DPU cable connector to prevent the card-side signals from floating when the RBT signals are isolated.

For DPUs, this pin should be connected between the connector and the RBT PHY.  External termination determined by the DPU RBT PHY requirements.

14

UART_TX

Input

3.3V UART TX signal from the baseboard

15

RBT_TXD1

Input

Transmit data. Data signals from the BMC to the network controller.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to GND on the baseboard between the RBT isolator and the DPU cable connector to prevent the card-side signals from floating when the RBT signals are isolated.

For DPUs, this pin should be connected between the connector and the RBT PHY.  External termination determined by the DPU RBT PHY requirements.

16

UART_RX

Output

3.3V UART RX signal to the baseboard

17

PRESENCE_N

Presence of DPU. Baseboard should implement a 200 Ω series resistor and 4.7kohm pull-up resistor to 3.3V AUX.

DPU should tie this to GND.

18

GND

GND

Ground

19

RBT_ARB_OUT

Input

NC-SI hardware arbitration output.

If the baseboard supports multiple DPUs cards connected to the same RBT interface, it should implement logic that connects the RBT_ARB_OUT pin of the first populated DPU card to its RBT_ARB_IN pin if it is the only card present or to the RBT_ARB_IN pin of the next populated card and so on sequentially for all cards on the specified RBT bus to ensure the arbitration ring is complete. This logic should bypass slots that are not populated or powered off.

20

RBT_ARB_IN

Output

NC-SI hardware arbitration input.

If the baseboard supports multiple DPUs cards connected to the same RBT interface, it should implement logic that connects the RBT_ARB_IN pin of the first populated  DPU card to its RBT_ARB_OUT pin if it is the only card present or to the RBT_ARB_OUT pin of the next populated card and so on sequentially for all cards on the specified RBT bus to ensure the arbitration ring is complete. This logic should bypass slots that are not populated or powered off.

1

GND 

GND BAR

1

2

PCIE_REFCLK1_P  

Micro coax 

38

2

3

PCIE_REFCLK1_N

Micro coax

38

3

4

GND 

GND BAR 

4

5

PCIE_CPU_CX_15N 

Micro coax

38 

5

6

PCIE_CPU_CX_15P

Micro coax

38 

6

7

GND  

GND BAR

7

8

PCIE_CPU_CX_14N

Micro coax

38

8

9

PCIE_CPU_CX_14P

Micro coax

38 

9

10

GND 

GND BAR

10

11

PCIE_CPU_CX_13N

Micro coax

38

11

12

PCIE_CPU_CX_13P

Micro coax

38

12

13

GND 

GND BAR

13

14

PCIE_CPU_CX_12N

Micro coax

38

14

15

PCIE_CPU_CX_12P

Micro coax

38

15

16

GND 

GND BAR

16

17

PCIE_CPU_CX_11N

Micro coax

38

17

18

PCIE_CPU_CX_11P

Micro coax

38

18

19

GND 

GND BAR

19

20

PCIE_CPU_CX_10N

Micro coax

38

20

21

PCIE_CPU_CX_10P

Micro coax

38

21

22

GND 

GND BAR

22

23

PCIE_CPU_CX_9N 

Micro coax

38

23

24

PCIE_CPU_CX_9P

Micro coax

38

24

25

GND 

GND BAR

25

26

PCIE_CPU_CX_8N

Micro coax

38

26

27

PCIE_CPU_CX_8P

Micro coax

38

27

28

GND 

GND BAR

28

29

PCIE_CPU_CX_7N 

Micro coax

38

29

30

PCIE_CPU_CX_7P 

Micro coax

38

30

31

GND 

GND BAR

31

32

CIE_CPU_CX_6N

Micro coax

38

32

33

PCIE_CPU_CX_6P

Micro coax

38

33

34

GND 

GND BAR

34

35

PCIE_CPU_CX_5N

Micro coax

38

35

36

PCIE_CPU_CX_5P

Micro coax

38

36

37

GND 

GND BAR

37

38

PCIE_CPU_CX_4N

Micro coax

38

38

39

PCIE_CPU_CX_4P 

Micro coax

38

39

40

GND 

GND BAR

40

41

PCIE_CPU_CX_3N

Micro coax

38

41

42

PCIE_CPU_CX_3P

Micro coax

38

42

43

GND 

GND BAR

43

44

PCIE_CPU_CX_2N

Micro coax

38

44

45

PCIE_CPU_CX_2P

Micro coax

38

45

46

GND 

GND BAR

46

47

PCIE_CPU_CX_1N

Micro coax

38

47

48

PCIE_CPU_CX_1P

Micro coax

38

48

49

GND 

GND BAR

49

50

PCIE_CPU_CX_0N

Micro coax

38

50

51

PCIE_CPU_CX_0P

Micro coax

38

51

52

GND 

GND BAR

52

53

No wire

Micro coax

38

53

54

No wire

Micro coax

38

54

55

AUX_PGOOD

Micro coax

38

55

56

No wire

Micro coax

38

56

57

I2C_AUX_SCL

Micro coax

38

57

58

I2C_AUX_SDA

Micro coax

38

58

59

S_PRSNT1_L 

Micro coax

38

59

60

No wire

60

1

No wire

Micro coax

38

1

2

No wire

Micro coax

38

2

3

No wire

Micro coax

38

3

4

No wire

Micro coax

38

4

5

No wire

Micro coax

38

5

6

Reserved_06

Micro coax

38

6

7

Reserved_07

Micro coax

38

7

8

Reserved_08

Micro coax

38

8

9

GND 

GND BAR

9

10

PCIE_CPU_CX_0P

Micro coax

38

10

11

PCIE_CPU_CX_0N

Micro coax

38

11

12

GND 

GND BAR

12

13

PCIE_CPU_CX_1P

Micro coax

38

13

14

PCIE_CPU_CX_1N

Micro coax

38

14

15

GND 

GND BAR

15

16

PCIE_CPU_CX_2P

Micro coax

38

16

17

PCIE_CPU_CX_2N

Micro coax

38

17

18

GND 

GND BAR

18

19

PCIE_CPU_CX_3P

Micro coax

38

19

20

PCIE_CPU_CX_3N

Micro coax

38

20

21

GND 

GND BAR

21

22

PCIE_CPU_CX_4P

Micro coax

38

22

23

PCIE_CPU_CX_4N

Micro coax

38

23

24

GND 

GND BAR

24

25

PCIE_CPU_CX_5P

Micro coax

38

25

26

PCIE_CPU_CX_5N

Micro coax

38

26

27

GND 

GND BAR

27

28

PCIE_CPU_CX_6P

Micro coax

38

28

29

PCIE_CPU_CX_6N

Micro coax

38

29

30

GND 

GND BAR

30

31

PCIE_CPU_CX_7P

Micro coax

38

31

32

PCIE_CPU_CX_7N

Micro coax

38

32

33

GND 

GND BAR

33

34

PCIE_CPU_CX_8P

Micro coax

38

34

35

PCIE_CPU_CX_8N

Micro coax

38

35

36

GND 

GND BAR

36

37

PCIE_CPU_CX_9P

Micro coax

38

37

38

PCIE_CPU_CX_9N

Micro coax

38

38

39

GND 

GND BAR

39

40

PCIE_CPU_CX_10P

Micro coax

38

40

41

PCIE_CPU_CX_10N

Micro coax

38

41

42

GND 

GND BAR

42

43

PCIE_CPU_CX_11P

Micro coax

38

43

44

PCIE_CPU_CX_11N

Micro coax

38

44

45

GND 

GND BAR

45

46

PCIE_CPU_CX_12P

Micro coax

38

46

47

PCIE_CPU_CX_12N

Micro coax

38

47

48

GND 

GND BAR

48

49

PCIE_CPU_CX_13P

Micro coax

38

49

50

PCIE_CPU_CX_13N

Micro coax

38

50

51

GND 

GND BAR

51

52

PCIE_CPU_CX_14P

Micro coax

38

52

53

PCIE_CPU_CX_14N

Micro coax

38

53

54

GND 

GND BAR

54

55

PCIE_CPU_CX_15P

Micro coax

38

55

56

PCIE_CPU_CX_15N

Micro coax

38

56

57

GND 

GND BAR

57

58

S_PERST1_CONN_L

Micro coax

38

58

59

No wire

No Wire

59

60

S_PRSNT2_L

Micro coax

38

60